1. Field of the Invention
The present invention relates to an integrated circuit device including a memory circuit which needs to preserve its content, namely, a DRAM.
2. Description of the Background Art
FIG. 6 is a circuit diagram showing a background-art circuit including a microcontroller. In the background-art circuit configuration, the microcontroller including a CPU 1 and a DRAM 2 are not integrated on the same chip, and a combination of the CPU 1 and the DRAM 2 on different chips is adopted. A cache 6 is integrated on the same chip as the CPU 1, separately from the DRAM 2.
In this system configuration, to put the system into standby mode (in which both the CPU 1 and the DRAM 2 are suspended) for low power consumption, a user has to do the following procedures in sequence:
Procedure 1) to perform a purge of the cache 6;
Procedure 2) to perform a preservation of the content of the DRAM 2 with the DRAM 2 set into self-refresh mode by accessing a DRAM controller; and
Procedure 3) to put the CPU 1 into suspend mode.
If an interrupt is requested between Procedure 2 and Procedure 3, for example, the CPU 1 remains in action while the DRAM 2 in the self-refresh mode can not be accessed. In this case, there is a possibility that an access request may be issued to the DRAM 2 by the CPU 1 resulting in no response. That should be avoided.
The user has to take some countermeasures, e.g., setting the circuit of FIG. 6 in the interrupt disabled mode during the above Procedures, to prevent the ordinary operation performed in an unfinished state of Procedures 1 to 3. Such countermeasures put a burden on the user and make an operability of the microcontroller worse.